This invention relates to a destuff circuit for eliminating stuffed dummy pulses included in received digital signals.
In time-division multiple channel transmission of digital signals, clock frequency of a channel to be transmitted is not generally synchronized to the system clock of the transmission. A buffer memory is provided for synchronizing digital signals of the channel to the system clock of the transmission. The digital signals of the channel are written in the buffer memory at the channel clock frequency. Contents of the buffer memory are read out at the system clock frequency. A data written at an address of the buffer memory is read out with an amount of time lag from the time of writing. As the system clock frequency is selected to be higher than the channel clock frequency, the amount of the time lag decreases as the reading of the buffer memory proceeds. When the amount of the time lag becomes less than a predetermined threshold value, reading of the buffer memory is interrupted and a dummy pulse or a train of dummy pulses is stuffed at the system clock frequency in the transmission signal of the channel.
During the time when stuffed pulses are transmitted, the digital signals of the channel are continually written in the buffer memory, increasing the time lag between the point of writing and that of reading of a data.
This system of stuffing dummy pulses at a transmitting site is called a positive stuffing system(P-stuff). There is another stuffing system called a negative stuffing system(N-stuff). In an N-stuff, channel data are previously stuffed with dummy pulses, and are written in the buffer memory including the stuffed dummy pulses at a writing frequency. The data in the buffer memory are read at a reading frequency which is lower than the writing frequency. The time lag between writing and reading of a data increases as the reading of the buffer memory proceeds. When the amount of the time lag becomes larger than a predetermined threshold, a dummy pulse or dummy pulses in the channel is(are) skipped to decrease the amount of the time lag. In a receiving site, these skipped pulses are reinserted.
Thus, a major difference between P-stuff and N-stuff is in addition or subtraction of dummy pulses, and many circuits used in P-stuff can be equally used in N-stuff with minor modifications. In the following descriptions, the present invention is described as an invention used in P-stuff, but it must be understood that the present invention can also be applied in N-stuff.
In many cases, a data is composed of a byte(a group of eight bits) of data pulses, and one data is stored in the buffer memory at an address of the buffer memory. In these cases, dummy pulses are stuffed in a byte unit. For example, SONET(synchronous optical network) system employs byte unit stuffed pulses for multi-channel synchronous transmission. These stuffed pulses are eliminated at a receiving site, and the received channel is represented by signal pulses uniformly distributed at the original clock frequency of the channel.
The elimination of stuffed pulses at a receiving site and the reproduction of the digital signals at the original clock frequency of the channel is called destuffing. A heretofore known destuffing circuit will be explained in connection with FIG. 3.
At a receiving site, received data of a channel, system clock pulses, destuff control signals in the channel are separated from received digital signals. The data of the channel(including stuffed dummy pulses) are delivered on an input data line 11, the system clock pulses are delivered on an input clock line 12, and the destuff control signals of the channel are delivered on a destuff control line 13.
Write address for writing the received data in the buffer memory 30 is generated in a write address counter 16 by the system clock pulses. It will be assumed in the following descriptions that a data is composed of eight data bits(or eight dummy bits) and two service bits, one service bit being a data synchronizing bit and the other service bit being a destuff control bit. Logic .left brkt-top.0.right brkt-bot. of the destuff control bit means that the data is a real data and logic .left brkt-top.1.right brkt-bot. of the destuff control bit means that the data is a byte of stuffed pulses.
Further, it is assumed that the data of the channel received in a bit serial form are converted to a train of data by a series parallel converter(not shown in the drawing), each data being composed of eight parallel pulses, and the train of data is transmitted on the input data line 11 composed of eight parallel lines; and that the clock pulses on the input clock line 12 are address clock pulses generated at a frequency divider(not shown in the drawing) from bit clock pulses extracted from received signals.
When a destuff control signal is a logic .left brkt-top.1.right brkt-bot. signal in a form of a gate pulse, the corresponding address clock pulse is prohibited by gates 14 and 15 from entering in a write address counter 16. And during the gate of the destuff control signal, write enable signal(not shown in the drawing) is disabled.
Thus, the stuffed dummy pulses are eliminated, and the change rate of the output of the write address counter 16, when the change rate is averaged, corresponds to the original clock frequency of the channel before the dummy pulses are stuffed. A VCO(voltage controlled oscillator) 34 generates a train of pulses of a frequency controlled by the output of an LPF(low pass filter) 33. The output of the VCO 34 controls the change rate of the output of a read address counter 31.
A phase detector 32, the LPF 33, the VCO 34, and the read address counter 31 compose a PLL(phase lock loop), and the change rate of the output of the read address counter 31 is controlled to be equal to the average value of the change rate of the output of the write address counter 16. Thus, the contents of the buffer memory 30 are read out on an output data line 35 at the rate of the original clock frequency of the channel.
The destuff circuit of FIG. 3 has problems in jitter elimination. The jitter effect in the destuff circuit of FIG. 3 is shown, in an exaggerated form, in FIG. 4. In FIG. 4, the address clocks on the input clock line 12 are denoted by numeral 41, and the data of the channel are denoted by numeral 42. The data of the channel 42 includes three real data A,B,C which have logic .left brkt-top.0.right brkt-bot. destuff control signals and three stuffed dummy data S1, S2, S3 which have logic .left brkt-top.1.right brkt-bot. destuff control signals in a duration of P.
The output of the write address counter 16 changes as shown by numeral 43, and the three real data A,B,C are written in the buffer memory 30. The address pulses generated from the output of the VCO 34 must be three pulses evenly distributed as denoted by numeral 44 in the time duration P and the output of the read address counter 31 changes as shown by numeral 45. The phase detector 32 detects phase differences between the output change points of the write address counter 16 and the corresponding output change points of the read address counter 31, that is, from 43a to 45a, from 43b to 45b, and from 43c to 45c.
These phase differences are converted to voltage differences usually represented by rectangular voltages of different duration, and high frequency components included in these rectangular voltages are attenuated in the LPF 33 to produce a direct-current voltage for controlling the frequency generated by the VCO 34. But, when the data of a channel are as shown by numeral 42, the output level of the phase detector 32 changes corresponding to the change of the phase differences as denoted by 43a-45a, 43b-45b, 43c-45c. This change of the output level of the phase detector 32 contains relatively low frequency components which are not filtered by the LPF 33. These low frequency components causes jitter in the generated frequency of the VCO 34.
When the stuffed dummy data are uniformly distributed as denoted by numeral 46, the output of the write address counter 16 changes as denoted by numeral 47, the detected phase differences are maintained practically constant as shown by 47a-45a, 47b-45b, 47c-45c. In this progress of phase differences, no low frequency components are included in the detected phase difference and jittering of the generated frequency is eliminated. When the output of the read address counter 31 has no jittering, there is no jittering in the output data on the output data line 35.
Therefore, it will be said that a uniform distribution of stuffed dummy data can prevent jittering of destuffed output pulses. As a prior art of this invention, there is a Japanese patent application entitled "Destuff system" and laid open as a provisional publication No. 188127/'89. In this prior art, two sets of buffer memories are used. In a first buffer memory, data of a channel is written destuffed by a destuff circuit which is similar to the circuit shown in FIG. 3. Then the first buffer memory is read out by read address signals generated by clock pulses having a frequency slightly higher than that of the clock pulses of the channel. The difference of the writing frequency and the reading frequency is compensated by stuffing uniformly distributed dummy signals. The read out data stuffed with uniformly distributed dummy signals are written in a second buffer memory. The second buffer memory is read out by a clock frequency which is precisely synchronized to the channel frequency by a destuff circuit which is similar to the destuff circuit shown in FIG. 3. Since stuffed dummy data are uniformly distributed in the input data of the second buffer memory, there is no jitter in the output data of the second buffer memory.
Thus, the destuff system of the prior art requires two sets of buffer memories for eliminating jitter in the output data, and this is a demerit of the system.